Traditional alternating-current (AC) coupled interconnect circuits are used for distributing clocks or other signals that are characterized by regular switching rates. A conventional interconnect circuit is illustrated in FIG. 1. The conventional interconnect circuit 10 is located on a printed circuit assembly 5 and includes a direct-coupled (DC) blocking capacitor 12 and a DC-bias network 14. The interconnect circuit 10 is inserted between a clock source 6 and an integrated circuit package 8 that uses a clock signal generated by the clock source 6. The interconnect circuit 10 has an input node 11 and an output node 17. The input node 11 is coupled to the clock source 6. The output node 17 is coupled to the integrated circuit package 8. The DC-blocking capacitor 12 is coupled between the input node 11 and the output node 17. The DC-bias network 14 includes a first branch 16 coupled between the output node 17 and a supply voltage, labeled VDD and a second branch 18, coupled between the output node 17 and a second voltage, labeled VSS. In an example embodiment, VDD is 1.0 Volts, VSS is 0.0 Volts and the first branch 16 and the second branch 18 of the DC-bias network 14 each include a resistor with an electrical resistance of R1 Ohms.
FIG. 2 includes a graphical representation of an input signal (i.e., a signal from the clock source 6) and an output signal (i.e., a signal at the IC package) for the interconnect circuit 10 of FIG. 1. FIG. 2 represents time along the horizontal axis and electrical potential in volts along the vertical axis. The input signal is represented by trace 21. The output signal is represented by trace 27. The input signal, as represented by trace 21, is a time-varying and periodic signal that begins at approximately 0.8 V and transitions over a relatively brief duration of time to approximately 1.5 V, where it remains for a longer duration of time or a peak interval before returning to 0.8 V. Trace 21 has a peak-to-peak voltage of approximately 0.7 V and a common-mode or average voltage of approximately 1.15 V. The input signal is symmetric about the common-mode voltage.
The output signal, as represented by trace 27, is a time-varying and periodic signal that is offset in voltage from the input signal. The output signal begins at approximately 0.15 V and transitions over the same relatively short interval, during which the input signal transitioned, until the output signal is approximately 0.85 V. The output signal remains at 0.85 V during a peak interval that corresponds to the peak interval of the input signal before returning to 0.15 V. The output signal, as represented by trace 27, has approximately the same peak-to-peak voltage (i.e., 0.7 V) as that of the input signal. However, the common-mode voltage of the output signal is about 0.5 V, which is approximately 0.6 V lower than the common-mode voltage of the input signal. The common-mode voltage of the output signal is determined by the voltage difference between the supply voltage, or VDD, and the second voltage, or VSS and the resistance values of the resistors in the first branch 16 and the second branch 18 of the DC-bias network 14.
Thus, the DC-blocking capacitor 12 of the conventional interconnect circuit 10 isolates the DC bias of two circuits. Stated another way, the interconnect circuit 10 shifts the common-mode voltage of a time-varying and periodic signal to an integrated circuit bias voltage. As illustrated by the trace 21 and the trace 27, the relative timing, the peak-to-peak voltage and the slew or transition rate remains unchanged by the interconnect circuit 10.
When the input signal fails to transition, such as when a clock signal is halted or interrupted, the DC-bias network 14 will charge/discharge the DC blocking capacitor 12 to the DC-bias voltage (i.e., (VDD−VSS)/2). For clock applications this is an undesirable behavior. When a differential clock signal with two AC-coupled inputs using the interconnect circuit 10 of FIG. 1A, encounters an interruption in the clock signal, such as when the input signal is halted (i.e., when the input signal no longer transitions), the true and complimentary signals at the respective output nodes of the interconnect circuits will exponentially decay and exponentially charge until the true and complimentary output signals reach the DC-bias voltage. As a result, a differential amplifier driven by those output nodes can generate undesired glitches or errors in the presence of electrical noise. In addition, the presence of the interconnect circuits will prevent the clock receiver from receiving suitable true and complimentary signals for some time after the differential clock signals at the input have resumed.
Increasing the time constant of the DC-bias network 14, which is responsible for the exponential decay or exponential charge of the output voltage, is one possibility for suppressing or reducing clock signal errors introduced by the noise induced glitches in a clock receiver. However, this approach requires relatively large circuit elements and only increases the time that the clock receiver will not be susceptible to clock signal glitches induced by a clock halt as the clock cannot be halted indefinitely.
Another possible solution is to introduce a hysteresis response in the clock receiver. However, a hysteresis response will corrupt the duty cycle of the clock signal due to variations in the circuit device manufacturing process, voltage and temperature.